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CY7C1021BNV33
64 K x 16 Static RAM
64 K x 16 Static RAM
Features

Functional Description[1]
The CY7C1021BNV33 is a high-performance CMOS static RAM organized as 65,536 words by 16 bits. This device has an automatic power-down feature that significantly reduces power consumption when deselected. Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is written into the location specified on the address pins (A0 through A15). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A15). Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from memory will appear on I/O8 to I/O15. See the truth table at the back of this data sheet for a complete description of read and write modes. The input/output pins (I/O0 through I/O15) are placed in a high-impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), the BHE and BLE are disabled (BHE, BLE HIGH), or during a write operation (CE LOW, and WE LOW). The CY7C1021BNV33 is available in 400-mil-wide SOJ, standard 44-pin TSOP Type II, and 48-ball mini BGA packages.
3.3 V operation (3.0 V-3.6 V) High speed tAA = 15 ns CMOS for optimum speed/power Low Active Power 576 mW (max) Low CMOS Standby Power 1.80 mW (max) Automatic power-down when deselected Independent control of upper and lower bits Available in 44-pin TSOP II and 400-mil SOJ Available in a 48-ball Mini BGA package

Note 1. For guidelines on SRAM system design, please refer to the `System Design Guidelines' Cypress application note, available on the internet at www.cypress.com.
Cypress Semiconductor Corporation Document #: 001-06433 Rev. *C
*
198 Champion Court
*
San Jose, CA 95134-1709
* 408-943-2600 Revised March 8, 2011
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CY7C1021BNV33
Logic Block Diagram
DATA IN DRIVERS
A7 A6 A5 A4 A3 A2 A1 A0
ROW DECODER
64K x 16 RAM Array
SENSE AMPS
I/O0-I/O7 I/O8-I/O15
COLUMN DECODER BHE WE CE OE BLE
Selection Guide
-15 Maximum Access Time (ns) Maximum Operating Current (mA) Maximum CMOS Standby Current (mA) 15 160 0.5
Document #: 001-06433 Rev. *C
A8 A9 A10 A11 A12 A13 A14 A15
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CY7C1021BNV33
Contents
Pin Configurations ........................................................... 4 Maximum Ratings ............................................................. 5 Operating Range ............................................................... 5 Electrical Characteristics ................................................. 5 Capacitance ...................................................................... 5 AC Test Loads and Waveforms ....................................... 6 Switching Characteristics ................................................ 7 Data Retention Characteristics ....................................... 8 Data Retention Waveform ................................................ 8 Switching Waveforms ...................................................... 9 Read Cycle No. 1 ........................................................ 9 Read Cycle No. 2 (OE Controlled) .............................. 9 Write Cycle No. 1 (CE Controlled) ............................. 10 Write Cycle No. 2 (BLE or BHE Controlled) .............. 10 Write Cycle No. 2 (WE Controlled, OE LOW) ........... 11 Truth Table ...................................................................... 11 Ordering Information ...................................................... 12 Ordering Code Definitions ......................................... 12 Package Diagrams .......................................................... 13 Acronyms ........................................................................ 15 Document Conventions ................................................. 15 Units of Measure ....................................................... 15 Document History Page ................................................. 16 Sales, Solutions, and Legal Information ...................... 17 Worldwide Sales and Design Support ....................... 17 Products .................................................................... 17 PSoC Solutions ......................................................... 17
Document #: 001-06433 Rev. *C
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CY7C1021BNV33
Pin Configurations
SOJ / TSOP II Top View A4 A3 A2 A1 A0 CE I/O0 I/O1 I/O2 I/O3 VCC VSS I/O4 I/O5 I/O6 I/O7 WE A15 A14 A13 A12 NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23
A5 A6 A7 OE BHE BLE I/O15 I/O14 I/O13 I/O12 VSS VCC I/O11 I/O10 I/O9 I/O8 NC A8 A9 A10 A11 NC
Mini BGA Top View
1
BLE
2
OE
3
A0
4
A1
5
A2 CE I/O1
6
NC I/O0 I/O2
A B C D E F G H
I/O8 BHE I/O9 I/O10
A3
A5
A4
A6 A7 NC
VSS I/O11 NC VCC I/O12 NC I/O14 I/O13 A14 I/O15 NC NC A8 A12 A9
I/O3 VCC I/O4 VSS I/O6
A15 I/O6 A13 A10
WE I/O7 A11 NC
Document #: 001-06433 Rev. *C
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CY7C1021BNV33
Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested. Storage Temperature ............................... -65 C to +150 C Ambient Temperature with Power Applied .......................................... -55 C to +125 C Supply Voltage on VCC to Relative GND[2] ...-0.5 V to +4.6 V DC Voltage Applied to Outputs in High Z State[2] .................................. -0.5 V to VCC + 0.5 V DC Input Voltage[2] .............................. -0.5 V to VCC + 0.5 V Current into Outputs (LOW)......................................... 20 mA Static Discharge Voltage.......................................... > 2001 V (per MIL-STD-883, Method 3015) Latch-Up Current .................................................... > 200 mA
Operating Range
Range Industrial Ambient Temperature -40 C to +85 C VCC 3.3 V 10%
Electrical Characteristics
Over the Operating Range Parameter VOH VOL VIH VIL IIX IOZ ICC ISB1 ISB2 Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage[2] Input Load Current Output Leakage Current VCC Operating Supply Current Automatic CE Power Down Current --TTL Inputs Automatic CE Power Down Current --CMOS Inputs GND < VI < VCC GND < VI < VCC, Output Disabled VCC = Max, IOUT = 0 mA, f = fMAX = 1/tRC Max VCC, CE > VIH, VIN > VIH or VIN < VIL, f = fMAX Max VCC, CE > VCC - 0.3 V, VIN > VCC - 0.3 V or VIN < 0.3 V, f = 0 Test Conditions VCC = Min, IOH = -4.0 mA VCC = Min, IOL = 8.0 mA -15 Min 2.4 - 2.2 -0.3 -1 -1 - - - Max - 0.4 VCC + 0.3 V 0.8 +1 +1 160 40 500 Unit V V V V A A mA mA A
Capacitance[3]
Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25 C, f = 1 MHz Max 6 8 Unit pF pF
Notes 2. Minimum voltage is -2.0 V for pulse durations of less than 20 ns. 3. Tested initially and after any design or process changes that may affect these parameters.
Document #: 001-06433 Rev. *C
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CY7C1021BNV33
AC Test Loads and Waveforms
3.3 V OUTPUT 30 pF INCLUDING JIG AND SCOPE (a) R2 351 R 317 3.3 V OUTPUT 5 pF INCLUDING JIG AND SCOPE (b) 167 30 pF 1.73 V R2 351 GND
Rise Time: 1 V/ns
R 317 3.0 V
ALL INPUT PULSES 90% 10% 90% 10%
Fall Time: 1 V/ns
OUTPUT Equivalent to: THEVENIN EQUIVALENT
Document #: 001-06433 Rev. *C
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CY7C1021BNV33
Switching Characteristics[4]
Over the Operating Range Parameter READ CYCLE tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD tDBE tLZBE tHZBE WRITE tWC tSCE tAW tHA tSA tPWE tSD tHD tLZWE tHZWE tBW CYCLE[7] Write Cycle Time CE LOW to Write End Address Set-Up to Write End Address Hold from Write End Address Set-Up to Write Start WE Pulse Width Data Set-Up to Write End Data Hold from Write End WE HIGH to Low Z[6] WE LOW to High Z[5, 6] Byte Enable to End of Write 15 10 10 0 0 10 8 0 3 - 9 - - - - - - - - - 7 - ns ns ns ns ns ns ns ns ns ns ns Read Cycle Time Address to Data Valid Data Hold from Address Change CE LOW to Data Valid OE LOW to Data Valid OE LOW to Low Z OE HIGH to High CE HIGH to High Z[5, 6] Z[5, 6] CE LOW to Low Z[6] CE LOW to Power-Up CE HIGH to Power-Down Byte Enable to Data Valid Byte Enable to Low Z Byte Disable to High Z 15 - 3 - - 0 - 3 - 0 - - 0 - - 15 - 15 7 - 7 - 7 - 15 7 - 7 ns ns ns ns ns ns ns ns ns ns ns ns ns ns Description -15 Min Max Unit
Notes 4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V, and output loading of the specified IOL/IOH and 30-pF load capacitance. 5. tHZOE, tHZBE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads and Waveforms on page 6. Transition is measured 500 mV from steady-state voltage. 6. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 7. The internal write time of the memory is defined by the overlap of CE LOW, WE LOW and BHE / BLE LOW. CE, WE and BHE / BLE must be LOW to initiate a write, and the transition of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
Document #: 001-06433 Rev. *C
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CY7C1021BNV33
Data Retention Characteristics
Over the Operating Range (L version only) Parameter VDR ICCDR tCDR[9] tR[10] Description VCC for Data Retention Data Retention Current VCC = VDR = 2.0 V, CE > VCC - 0.3 V, VIN > VCC - 0.3 V or VIN < 0.3 V Conditions[8] Min 2.0 - Max - 100 Unit V A
Chip Deselect to Data Retention Time Operation Recovery Time
0 15
- -
ns ns
Data Retention Waveform
DATA RETENTION MODE VCC CE 3.0 V tCDR VDR > 2 V 3.0 V tR
Notes 8. No input may exceed VCC + 0.5 V. 9. Tested initially and after any design or process changes that may affect these parameters. 10. tr < 3 ns for the -12 and -15 speeds. tr < 5 ns for the -20 and slower speeds.
Document #: 001-06433 Rev. *C
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CY7C1021BNV33
Switching Waveforms
Read Cycle No. 1[11, 12]
tRC ADDRESS tOHA DATA OUT PREVIOUS DATA VALID tAA DATA VALID
Read Cycle No. 2 (OE Controlled)[12, 13]
ADDRESS tRC CE tACE OE BHE, BLE tDOE tLZOE tDBE tLZBE DATA OUT VCC SUPPLY CURRENT HIGH IMPEDANCE tLZCE tPU 50% DATA VALID tPD 50% tHZCE tHZBE tHZOE
HIGH IMPEDANCE
IICC CC IISB SB
Notes 11. Device is continuously selected. OE, CE, BHE and/or BHE = VIL. 12. WE is HIGH for read cycle. 13. Address valid prior to or coincident with CE transition LOW.
Document #: 001-06433 Rev. *C
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CY7C1021BNV33
Switching Waveforms(continued)
Write Cycle No. 1 (CE Controlled)[14, 15]
tWC ADDRESS
CE
tSA
tSCE
tAW tPWE WE tBW BHE, BLE tSD DATA I/O tHD
tHA
Write Cycle No. 2 (BLE or BHE Controlled)
tWC ADDRESS
BHE, BLE
tSA
tBW
tAW tPWE WE tSCE CE tSD DATA I/O tHD
tHA
Notes 14. Data I/O is high impedance if OE or BHE and/or BLE= VIH. 15. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
Document #: 001-06433 Rev. *C
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CY7C1021BNV33
Switching Waveforms(continued)
Write Cycle No. 2 (WE Controlled, OE LOW)
tWC ADDRESS
CE
tSCE
tAW tSA WE tBW BHE, BLE tHZWE DATA I/O tSD tHD tPWE
tHA
tLZWE
Truth Table
CE H L OE X L WE X H BLE X L L H L X L L L H L L H X H X X H BHE X L H L L H L X H I/O0-I/O7 High Z Data Out Data Out High Z Data In Data In High Z High Z High Z I/O8-I/O15 High Z Data Out High Z Data Out Data In High Z Data In High Z High Z Power-Down Read - All bits Read - Lower bits only Read - Upper bits only Write - All bits Write - Lower bits only Write - Upper bits only Selected, Outputs Disabled Selected, Outputs Disabled Mode Power Standby (ISB) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC)
Document #: 001-06433 Rev. *C
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CY7C1021BNV33
Ordering Information
Cypress offers other versions of this type of product in many different configurations and features. The following table contains only the list of parts that are currently available. For a complete listing of all options, visit the Cypress website at http://www.cypress.com and refer to the product summary page at http://www.cypress.com/products or contact your local sales representative. Cypress maintains a worldwide network of offices, solution centers, manufacturer's representatives and distributors. To find the office closest to you, visit us at http://www.cypress.com/go/datasheet/offices. Speed (ns) 15 Ordering Code CY7C1021BNV33L-15BAI CY7C1021BNV33L-15VXI CY7C1021BNV33L-15ZXI Package Diagram 51-85096 51-85082 51-85087 Package Type 48-ball Mini BGA (7 mm x 7 mm) 44-pin (400-Mil) Molded SOJ (Pb-free) 44-pin TSOP Type II (Pb-free) Operating Range Industrial
Ordering Code Definitions
CY 7 C 1 02 1 BN V33 L - 15 XX I Temperature Range: I = Industrial Package Type: XX = BA or VX or ZX BA = 48-ball Mini BGA VX = 44-pin Molded SOJ (Pb-free) ZX = 44-pin TSOP Type II (Pb-free) Speed: 15 ns L = Low power V33 = Voltage range (3 V to 3.6 V) BN = 0.25 m Technology 1 = Data width x 16-bits 02 = 1-Mbit density 1 = Fast Asynchronous SRAM family Technology Code: C = CMOS 7 = SRAM CY = Cypress
Please contact local sales representative regarding availability of these parts.
Document #: 001-06433 Rev. *C
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CY7C1021BNV33
Package Diagrams
Figure 1. 48-ball FBGA (7 mm x 7 mm x 1.2 mm), 51-85096
51-85096 *I
Figure 2. 44-pin (400-Mil) Molded SOJ, 51-85082
51-85082 *C
Document #: 001-06433 Rev. *C
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CY7C1021BNV33
Package Diagrams(continued)
Figure 3. 44-pin TSOP Type II, 51-85087
51-85087 *C
Document #: 001-06433 Rev. *C
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CY7C1021BNV33
Acronyms
Acronym BGA CMOS CE FBGA I/O OE SOJ SRAM TTL TSOP WE ball grid array complementary metal oxide semiconductor chip enable Fine-Pitch Ball Grid Array input/output output enable small outline J-lead static random access memory transistor-transistor logic thin small-outline package write enable Description
Document Conventions
Units of Measure
Symbol ns s V A mA mm MHz pF C % mW W nano seconds micro seconds ohms Volts micro Amperes milli Amperes milli meter Mega Hertz pico Farad degree Celcius percent milli Watts Watts Unit of Measure
Document #: 001-06433 Rev. *C
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CY7C1021BNV33
Document History Page
Document Title: CY7C1021BNV33 64 K x 16 Static RAM Document Number: 001-06433 REV. ** *A *B *C ECN NO. 423847 2897061 3109897 3103073 Issue Date See ECN 03/22/10 12/14/2010 03/08/2011 Orig. of Change NXR AJU AJU PRAS Description of Change New Data Sheet Removed obsolete parts from ordering information table Updated package diagrams Added Ordering Code Definitions Updated Package Diagrams. Added Acronyms and Units of Measure. Updated in new template.
Document #: 001-06433 Rev. *C
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CY7C1021BNV33
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer's representatives, and distributors. To find the office closest to you, visit us at Cypress Locations.
Products
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PSoC Solutions
psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 5
(c) Cypress Semiconductor Corporation, 2006-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress' product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 001-06433 Rev. *C
Revised March 8, 2011
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